Advancements in semiconductor manufacture have led to increases in the density and miniaturization of microelectronic circuits. As an example, the manufacture of 1 Gb DRAMs is now possible and 4 Gb prototypes are currently being developed. A key requirement for achieving such high device packing density is the formation of suitable storage capacitors.
With increased packing density of memory cells, however, the area available for storage capacitors (i.e. storage nodes) has decreased. This has necessitated the development of storage capacitors having an increased capacitance. In general, storage capacitors can be formed as stacked structures or as trench structures. The present invention is directed in part to stacked structures and in another part to a combination stacked-trench structure.
Typically, a thin film stacked storage capacitor includes a lower electrode, an upper electrode, and a dielectric layer which is sandwiched between the electrodes. This capacitor structure is stacked on an insulating layer of a substrate. The insulating layer is typically formed from materials such as SiO.sub.2 and Si.sub.3 N.sub.4 that are compatible with a silicon process. The lower electrode of the capacitor is connected to a field effect transistor (FET) formed on the substrate. A polycrystalline silicon layer has been used as the lower electrode of a capacitor. Such a polysilicon layer is sometimes referred to as a polysilicon or silicon electrode.
One way to increase the capacity of this type of capacitor is to use a dielectric layer formed with a high dielectric constant material. These high dielectric constant materials include inorganic non-metallic oxides in the paraelectric or ferro electric phase such as BaSrTiO.sub.3 (BST), BaTiO.sub.3, SrTiO.sub.3, PbZrO.sub.3 and others. Such high dielectric constant materials have a dielectric constant greater than 100. This is an order of magnitude larger than traditional dielectric materials, such as SiO.sub.2 and Si.sub.3 N.sub.4, which have dielectric constants less than 10.
A problem with high capacitance capacitors is that generally high dielectric constant films cannot be formed directly over a polysilicon electrode. This is because an interface layer of silicon dioxide forms between the dielectric film and the polysilicon electrode. Such an interface layer reduces the effective dielectric constant of the dielectric material and defeats its purpose. For this reason, the lower electrode structure is typically formed as a stack comprising a barrier layer formed on the polysilicon electrode and a lower electrode formed on the barrier layer.
The barrier layer is typically formed from a conductive material, such as tantalum (Ta), titanium nitride (TiN), or tungsten nitride (WN). Such a barrier layer, in addition to preventing oxidation of the polysilicon electrode, also functions to prevent silicon diffusion into the lower electrode. Such silicon diffusion increases the resistivity of the lower electrode and could lead to the formation of a thin layer of SiO.sub.2 layer on top of the lower electrode.
Another problem associated with the use of high dielectric constant films is that these films must be deposited at relatively high temperatures (e.g. 600.degree. C. to 700.degree. C.). Because of the high process temperatures that are required, the lower electrode of such a capacitor is typically formed of a high melting point, non-oxidizing metal such as platinum, palladium or rhodium or of a conducting oxide such as ruthenium oxide, iridium oxide, osmium oxide or rhodium oxide. A non-oxidizing material is required for the lower electrode because a traditional electrode material such as aluminum, titanium, nichrome or copper will oxidize at the high temperatures, increasing the resistivity of the electrode.
A prior art stacked capacitor 10 employing a high dielectric constant dielectric film 26 is shown in FIG. 1. In FIG. 1, a semiconductor substrate 12 includes a FET (not shown) formed with a pair of insulated gate electrodes 14 and 16. An insulating layer 18 is formed over the FET and gate electrodes 14 and 16. The capacitor 10 is stacked on the insulating layer 18. A polysilicon plug 20 is formed in a contact hole formed through the insulating layer 18 to the source or drain region 30 of the FET.
The capacitor 10 includes a lower electrode 22 having a rectangular cross section, an upper electrode 24 and a dielectric film 26 formed between the lower electrode 22 and the upper electrode 24. The capacitor 10 also includes a barrier layer 28 formed between the lower electrode 22 and the polysilicon plug 20.
Such a capacitor is subject to several limitations. First, the dielectric layer 26 must be formed over the stepped surface contour provided by the stack formed by the lower electrode 22 and the barrier layer 28. Poor step coverage of the dielectric material 28 over the lower electrode 22 promotes charge leakage at the corners of the dielectric material 26 in the completed capacitor structure. To prevent this leakage, an insulating material such as silicon dioxide is sometimes deposited over the outside corners of the dielectric film 26.
Second, the sidewalls 34 and 36 of the barrier layer 28 are exposed to oxidation during deposition of the dielectric film 26. Accordingly, the high temperatures encountered during the dielectric deposition process will cause the sidewalls of the barrier layer 28 to oxidize. Such an oxide increases the contact resistance of the barrier layer 28. Further, with an oxide formed on the sidewalls 34 and 36 of the barrier layer 28, the lower electrode 22 will not adhere as well to the barrier layer 28 which results in the lower electrode 22 separating from the barrier layer 28.
Third, if the barrier layer 28 does not completely overlap the polysilicon plug 20, then the surface of the polysilicon plug will oxidize during the deposition of the dielectric material 26. A critical alignment of the barrier layer 28 and the polysilicon plug 20 is required.
A solution to these problems is provided by U.S. Pat. No. 5,335,138 to Sandhu et al. This patent teaches the use of spacers positioned at each end of the lower electrode-barrier layer stack to prevent oxidation of the sidewalls of the barrier layer during deposition of the dielectric film. These spacers also provide a smooth topography for the deposition of the dielectric film. This provides the completed capacitor with a smooth topography which prevents the current leakage which occurs through sharp corners of the dielectric layer. Finally, the spacers provide a larger area for protection of the polysilicon plug from oxidation. However, the process described by Sandhu et al. requires additional processing steps and time to form the spacers.
For these reasons, a need exists in the art for a capacitor which is not subject to the limitations of the prior art. Particularly, a need exists in the art for a capacitor and a method for making a capacitor which has step coverage which eliminates charge leakage. A need also exists for a capacitor and a method for making a capacitor which prevents oxidation of the sidewalls of the lower electrode and the barrier layer. Another need exists for a capacitor and a method for making a capacitor which provide for proper placement of the lower electrode and barrier layer over the polysilicon plug. Finally, a need exists in the art for a method of making such a capacitor which will quickly and efficiently address the current needs in the art.